System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
Path C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\12.3\ISE_DS\common\bin\nt64;
C:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\MiKTeX 2.9\miktex\bin;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\jEdit;
C:\Program Files\Java\jdk1.6.0_18\bin;
C:\Program Files\MATLAB\R2009b\runtime\win64;
C:\Program Files\MATLAB\R2009b\bin;
C:\yagarto\bin;
C:\Program Files (x86)\Pico Technology\PicoScope6\;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\OpenVPN\bin;
C:\Modeltech_pe_edu_6.6d\win32pe_edu
C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\12.3\ISE_DS\common\bin\nt64;
C:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\MiKTeX 2.9\miktex\bin;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\jEdit;
C:\Program Files\Java\jdk1.6.0_18\bin;
C:\Program Files\MATLAB\R2009b\runtime\win64;
C:\Program Files\MATLAB\R2009b\bin;
C:\yagarto\bin;
C:\Program Files (x86)\Pico Technology\PicoScope6\;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\OpenVPN\bin;
C:\Modeltech_pe_edu_6.6d\win32pe_edu
C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\12.3\ISE_DS\common\bin\nt64;
C:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\MiKTeX 2.9\miktex\bin;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\jEdit;
C:\Program Files\Java\jdk1.6.0_18\bin;
C:\Program Files\MATLAB\R2009b\runtime\win64;
C:\Program Files\MATLAB\R2009b\bin;
C:\yagarto\bin;
C:\Program Files (x86)\Pico Technology\PicoScope6\;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\OpenVPN\bin;
C:\Modeltech_pe_edu_6.6d\win32pe_edu
C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\12.3\ISE_DS\common\bin\nt64;
C:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\MiKTeX 2.9\miktex\bin;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\jEdit;
C:\Program Files\Java\jdk1.6.0_18\bin;
C:\Program Files\MATLAB\R2009b\runtime\win64;
C:\Program Files\MATLAB\R2009b\bin;
C:\yagarto\bin;
C:\Program Files (x86)\Pico Technology\PicoScope6\;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\OpenVPN\bin;
C:\Modeltech_pe_edu_6.6d\win32pe_edu
XILINX C:\Xilinx\12.3\ISE_DS\ISE\ C:\Xilinx\12.3\ISE_DS\ISE\ C:\Xilinx\12.3\ISE_DS\ISE\ C:\Xilinx\12.3\ISE_DS\ISE\
XILINX_DSP C:\Xilinx\12.3\ISE_DS\ISE C:\Xilinx\12.3\ISE_DS\ISE C:\Xilinx\12.3\ISE_DS\ISE C:\Xilinx\12.3\ISE_DS\ISE
XILINX_EDK C:\Xilinx\12.3\ISE_DS\EDK C:\Xilinx\12.3\ISE_DS\EDK C:\Xilinx\12.3\ISE_DS\EDK C:\Xilinx\12.3\ISE_DS\EDK
XILINX_PLANAHEAD C:\Xilinx\12.3\ISE_DS\PlanAhead C:\Xilinx\12.3\ISE_DS\PlanAhead C:\Xilinx\12.3\ISE_DS\PlanAhead C:\Xilinx\12.3\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   LATop.prj  
-ifmt   mixed Mixed
-ofn   LATop  
-ofmt   NGC NGC
-p   xc6slx45-2-csg324  
-top   LATop  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 2 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy Soft No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-sd Cores Search Directories {"ipcore_dir" }  
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis YES No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   YES No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   16 16
-register_duplication   YES Yes
-register_balancing   Yes No
-move_first_stage   YES Yes
-move_last_stage   YES Yes
-optimize_primitives   NO No
-use_clock_enable   Auto Auto
-use_sync_set   Auto Auto
-use_sync_reset   Auto Auto
-iob   True Auto
-equivalent_register_removal   NO Yes
-slice_utilization_ratio_maxmargin   5 0
 
Translation Property Settings
Switch Name Property Name Value Default Value
-bm   D:/e-/logic-analyzer/BitHound/fpga/prog_mem.bmm None
-intstyle   ise None
-dd   _ngo None
-p   xc6slx45-csg324-2 None
-sd Macro Search Path ipcore_dir None
-uc   D:/e-/logic-analyzer/BitHound/fpga/LATop.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-detail Generate Detailed MAP Report TRUE TRUE
-ol Place & Route Effort Level (Overall) high high
-xe Placer Extra Effort Map NORMAL  
-xt Extra Cost Tables 0 0
-global_opt Global Optimization map TRUE FALSE
-ir Use RLOC Constraints ALL OFF
-ignore_keep_hierarchy Allow Logic Optimization Across Hierarchy TRUE FALSE
-logic_opt Combinatorial Logic Optimization TRUE FALSE
-t Starting Placer Cost Table (1-100) Map 1 0
-equivalent_register_removal Equivalent Register Removal FALSE TRUE
-register_duplication Register Duplication Map TRUE FALSE
-retiming Retiming TRUE FALSE
-intstyle   ise None
-lc LUT Combining auto off
-o   LATop_map.ncd None
-w   true false
-pr Pack I/O Registers/Latches into IOBs b off
-p   xc6slx45-csg324-2 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-xe   n None
-intstyle   ise  
-mt Enable Multi-Threading 4 off
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz/2808 MHz Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz/2808 MHz Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz/2808 MHz Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz/2808 MHz
Host lukas-PC lukas-PC lukas-PC lukas-PC
OS Name Microsoft Microsoft Microsoft Microsoft
OS Release Service Pack 1 (build 7601) Service Pack 1 (build 7601) Service Pack 1 (build 7601) Service Pack 1 (build 7601)