LATop Project Status (10/02/2011 - 12:33:41)
Project File: BitHoundDigilent.xise Parser Errors: No Errors
Module Name: LATop Implementation State: Programming File Generated
Target Device: xc6slx45-2csg324
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
1012 Warnings (1 new)
Design Goal: Timing Performance
  • Routing Results:
All Signals Completely Routed
Design Strategy: Performance with Physical Synthesis (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 7,849 54,576 14%  
    Number used as Flip Flops 7,849      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 7,244 27,288 26%  
    Number used as logic 6,532 27,288 23%  
        Number using O6 output only 4,868      
        Number using O5 output only 460      
        Number using O5 and O6 1,204      
        Number used as ROM 0      
    Number used as Memory 184 6,408 2%  
        Number used as Dual Port RAM 32      
            Number using O6 output only 4      
            Number using O5 output only 12      
            Number using O5 and O6 16      
        Number used as Single Port RAM 0      
        Number used as Shift Register 152      
            Number using O6 output only 12      
            Number using O5 output only 0      
            Number using O5 and O6 140      
    Number used exclusively as route-thrus 528      
        Number with same-slice register load 511      
        Number with same-slice carry load 17      
        Number with other load 0      
Number of occupied Slices 2,479 6,822 36%  
Number of LUT Flip Flop pairs used 8,542      
    Number with an unused Flip Flop 2,317 8,542 27%  
    Number with an unused LUT 1,298 8,542 15%  
    Number of fully used LUT-FF pairs 4,927 8,542 57%  
    Number of unique control sets 289      
    Number of slice register sites lost
        to control set restrictions
603 54,576 1%  
Number of bonded IOBs 134 218 61%  
    Number of LOCed IOBs 134 134 100%  
    IOB Flip Flops 42      
Number of RAMB16BWERs 24 116 20%  
Number of RAMB8BWERs 2 232 1%  
Number of BUFIO2/BUFIO2_2CLKs 2 32 6%  
    Number used as BUFIO2s 2      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 10 16 62%  
    Number used as BUFGs 8      
    Number used as BUFGMUX 2      
Number of DCM/DCM_CLKGENs 1 8 12%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 42 376 11%  
    Number used as ILOGIC2s 42      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 24 376 6%  
    Number used as IODELAY2s 0      
    Number used as IODRP2s 2      
    Number used as IODRP2_MCBs 22      
Number of OLOGIC2/OSERDES2s 45 376 11%  
    Number used as OLOGIC2s 0      
    Number used as OSERDES2s 45      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 1 4 25%  
Number of DSP48A1s 2 58 3%  
    Number of LOCed DSP48A1s 2 2 100%  
Number of ICAPs 0 1 0%  
Number of MCBs 1 2 50%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 2 4 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.67      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi 17. Aug 19:34:55 20110923 Warnings (0 new)381 Infos (1 new)
Translation ReportCurrentMi 17. Aug 19:35:08 2011058 Warnings (0 new)11 Infos (0 new)
Map ReportCurrentMi 17. Aug 19:58:53 201109 Warnings (0 new)57 Infos (0 new)
Place and Route ReportCurrentMi 17. Aug 20:01:46 2011013 Warnings (1 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMi 17. Aug 20:02:08 2011003 Infos (0 new)
Bitgen ReportCurrentSo 2. Okt 12:33:27 201109 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentMi 17. Aug 21:56:18 2011
Post-Synthesis Simulation Model ReportOut of DateSo 3. Jul 12:37:07 2011
Physical Synthesis ReportCurrentMi 17. Aug 19:58:53 2011
WebTalk ReportCurrentSo 2. Okt 12:33:28 2011
WebTalk Log FileCurrentSo 2. Okt 12:33:41 2011

Date Generated: 10/02/2011 - 12:33:41